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  1. #1
    Unregistered

    Share VLSI Interview questions.

    Share VLSI Interview questions.
    thank you..


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  3. #2
    jevirsinh
    Join Date
    Aug 2012
    Posts
    254

    Thumbs up Re: Share VLSI Interview questions.

    Hello
    VLSI stand for VERY LARGE SCALE INTEGRATED CIRCUIT


    please find attachment for VLSI interview question


    All the best
    Attached Files




  4. #3
    ASHWANI SINGH
    Join Date
    Jul 2012
    Posts
    211

    Re: Share VLSI Interview questions.

    hi friends

    VLSI interview questions are as follows:

    [COLOR="rgb(255, 0, 255)"]1. what is the difference between mealy and moore state-machines
    2. How to solve setup & Hold violations in the design
    3. What is antenna Violation & ways to prevent it
    4. We have multiple instances in RTL(Register Transfer Language), do you do
    anything special during synthesis stage?
    5. what is tie-high and tie-low cells and where it is used?
    6. what is the difference between latches and flip-flops based designs?
    7. What is High-Vt and Low-Vt cells.
    8. What is LEF mean?
    9. what is DEF mean?
    10. Steps involved in designing an optimal padring?
    11. What is metastability and steps to prevent it.
    12. what is local-skew, global-skew,useful-skew mean?
    13. What are the various timing-paths which i should take care in my STA runs?
    14. What are the various components of Leakage-power?
    15. What are the various yield-losses in the design?
    16. what is meant by virtual clock definition and why do i need it?
    17. What are the various Variations which impacts timing of the design?
    18. What are the various Design constraints used while performing Synthesis for a
    design?
    19. Specify few verilog constructs which are not supported by the synthesis tool.
    20.what are the various capacitances with an MOSFET?
    21.Vds-Ids curve for an MOSFET, with increasing Vgs.
    22. Basic Operation of an MOSFET.
    23. What is Channel length Modulation?
    24. what is body effect?
    25. What is latchup in CMOS design and ways to prevent it?
    [/COLOR]
    Attached Files

  5. #4
    ravikannth2027
    Join Date
    Jan 2012
    Location
    hyderabad
    Posts
    1,477

    Re: Share VLSI Interview questions.

    VLSI Interview Questions :



    What is difference between mealy & more state machines ?

    How to solve setup & hold Violations in the design ?

    What is antenna Violation & ways to prevent it ?

    We have multiple instances in RTL ?

    What is tie - high & tie - low cells & where it is used ?

    What is the difference between latches & flip - flops based designs ?

    What is high Vt & Low Vt Cells ?

    What is LEF mean ?

    Waht is DEF mean ?

    Steps involved in designing an optimal padring ?

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